Emulation systems typically were formed using emulation integrated circuits, including programmable logic devices (PLDs), such as general-purpose field programmable gate arrays (FPGAs), without integrating debugging facilities. To emulate a design on such an emulation system, the design would be “realized” by compiling a formal description of the design, partitioning the design into subsets, mapping various subsets to the logic elements (LEs) of the emulation integrated circuits of various logic boards of the emulations system, and then configuring various interconnects to interconnect the logic elements. The partitioning and mapping operations typically would be performed on workstations that were part of or complementary to the emulation systems, while the configuration information would be downloaded onto the logic boards hosting the emulation integrated circuits, and then onto the emulation integrated circuits.
There are various times in the operation of an emulation system, like many other systems, when it is desirable to test the circuitry of the emulation system to ensure it is functioning properly. For instance, when a system is first powered on, a series of tests are performed on the components of the system. Traditionally, as a microcontroller is first powered on, it will be directed to a location in its memory map where code is stored in read only memory (ROM). This code will typically cause the microcontroller to perform tests on itself and other components in the system containing the microcontroller to ascertain if the system is functioning properly.
In the case of an emulator, if the logic used to emulate a design is itself faulty, a user of the emulation system may be led astray by such faulty logic. The user may be falsely led to believe that the design is working properly. The user may also be falsely led to believe that a failure of a design to perform as expected in the emulator is due to a design failure of the design under verification. That is, when there is faulty emulation circuitry, the design may be proper while the faulty emulation logic causes the undesired results from the emulation. Accordingly, when an emulation system is powered on, the emulation system may perform a series of self-tests to ensure that at least the emulation system is working properly.
Later generations of emulation systems have employed emulation integrated circuits with increased density of reconfigurable logic and interconnects, which in turn, have increased the amount of time required to perform these self-tests. Commonly, self-testing involves processes similar to operation during emulation, as described above. In order to self-test components, such as reconfigurable interconnect integrated circuits, or a reconfigurable interconnect portion of an integrated circuit, a series of self-test stimuli are generated, and transferred to various logic boards for input into the integrated circuits. Each of the series of self-test stimuli tests a particular component or sub-component of the emulation system. Expected results from the self-test stimuli are compared with actual results from the self-test stimuli. That is, if even a single switch in a switching matrix is not functioning properly, the actual result from the self-test stimuli would vary from the expected result from the self-test stimuli.
Various problems can also occur with the reconfigurable interconnects. These problems include manufacturing and design defects that result in the cross-influence of signal lines in a device. Thus, due to an unintended short or gap that occurs in the device, one line in a reconfigurable interconnect device may influence another line to cause an erroneous value to appear on that other line. As the systems become more complex, the time associated with testing steps can greatly increase. These testing steps may result in systems requiring tens of minutes to hours to complete a self-test session. Only after self-testing is complete could actual design emulation begin. Any reduction in the amount of time in the design cycle is desirable. Moreover, an improved approach to testing reconfigurable devices to facilitate a series of self-tests is desired to avoid misidentified failures, which are costly to a design cycle.